Semiconductor device and manufacturing method thereof

ABSTRACT

The present invention provides a semiconductor device that reduces the junction leak current and achieves an improvement in the reliability of the gate oxide film by minimizing divot formation and the occurrence of a kink and a method of manufacturing such a semiconductor device. A pad oxide film and a silicon nitride film are formed on an Si substrate and a groove-like trench is formed through photolithography and etching. The liner oxide of the trench are oxidized through oxidizing/nitriding. Then, the trench is filled with an insulating film, the insulating film is planarized and the silicon nitride film and the pad oxide film are removed. Next, a field area is formed and a transistor is formed by following specific steps. By forming a trench liner oxide film containing nitrogen, stress is reduced.

BACKGROUND OF THE INVENTION

The present invention relates to a structure of an element isolationregion in a semiconductor device and a semiconductor devicemanufacturing method.

In a semiconductor device having silicon as its main constituent, anelement isolation region (hereafter referred to as a field area) isformed through the LOCOS (local oxidation of silicon) method or the STI(shallow trench isolation) method to electrically isolate elements inthe prior art. An area other than the field area is referred to as anactive area, and the elements are formed in the active area. When afield area is formed through the LOCUS method, a bird's beak is formedat an end of the field area, reducing the size of the area that can beutilized as active area. With further miniaturization of elementsachieved in recent years, the width and the pitch of the active areahave become smaller and the use of the LOCOS method to form the fieldarea is problematic. In contrast, the STI method, which by its naturecreates hardly any bird's beak, is considered to be a more viable methodof field area formation, achieving reduced conversion difference. FIG. 7illustrates the STI manufacturing method. As shown in FIG. 7(a), agroove referred to as a trench 7 is formed at a Si substrate 1. Then, asillustrated in FIG. 7(b), a trench liner oxide film 71 is formed at theinsidewalls of the trench 7 and the trench is filled with an embeddedinsulating film 72 such as a CVD oxide film to form a field area.

However, when the field area is formed by adopting the manufacturingmethod described above, a groove referred to as a divot 81, as shown inFIG. 8, is formed at the surface of the field area near the boundarywith the active area. As a result, the edge of the active area adjacentto the divot 81 becomes exposed. FIG. 8 is an enlarged view of the areaaround the edge. When this area becomes exposed, numerous problems arisewith regard to the occurrence of stress which is to be detailed later.

When a field area is formed through the STI method, the embeddedinsulating film 72 and the Si substrate 1 become expanded during theheat treatment performed after the trench is filled with the embeddedinsulating film 72. Since the embedded insulating film 72 and the Sisubstrate 1 have different coefficients of expansion, stress occurs attheir interface. In addition, stress also occurs at the interface of thetrench liner oxide film 71 formed through thermal oxidation and the Sisubstrate 1 as a result of volumetric expansion caused by the oxygenatoms occupying space between the Si atoms. These stresses occur nearthe boundary of the active area and the field area, and a particularlyintense stress occurs at the edges of the active area.

At the edge of an area of intense stress, accelerated diffusion ofimpurities occurs during the annealing process implemented after theimpurity ion implantation and, as illustrated in FIG. 8, the impurityconcentration at the edge becomes lowered compared to that around thecenter of the active area. If the edge becomes exposed as a result ofdivot formation, a parasitic transistor with a low threshold voltage isformed over the area with a low impurity concentration. In such a case,there will be a kink in the characteristics curve achieved by thetransistor, as shown in FIG. 9. In FIG. 9, the vehicle axis representsthe drain current Id and the horizontal axis represents the gate voltageVg. If there is no parasitic transistor present, the transistorcharacteristics curve is free of any kink. The presence of a kinkresults in electrical characteristics different from the designelectrical characteristics, and thus, the transistor characteristicscannot be identified. In addition, since parasitic transistors and kinksmanifesting under these circumstances are not uniform, the transistorcharacteristics cannot be determined with uniformity during theproduction, which, in turn, results in inconsistency in transistorcharacteristics.

Furthermore, occurrence of stress induces a dislocation, resulting inthe formation of crystal defects. When the impurity concentration isreduced, a depletion layer is more readily extended compared to theother areas, to lead to an increase in the junction leak current of viathe crystal defects.

An oxide film is not formed at the Si substrate isotropically and thedirection in which the oxide film is formed varies depending upon thedirection of the crystal. If the edge of the active area is exposed dueto the formation of a divot, the thickness of the oxide film formed atthe surface along the vertical direction of the edge becomes differentfrom the thickness of the oxide film formed at the surface along thehorizontal direction. The combination of this inconsistent oxide filmthickness and the stress occurring at the edge causes the thickness of agate oxide film 92 to become locally reduced over this area, as shown inFIG. 8. When the film thickness is reduced, the reliability of the gateoxide film 92 becomes an issue. In addition, the structure of this areais such that an electric field tends to concentrate in the area in thefirst place, and if the gate oxide film 92 becomes thinner over thearea, more electric field concentrates through a synergistic effect. Anelectric field concentration is considered to be one of the causes ofkinks and is, therefore, not desirable.

SUMMARY OF THE INVENTION

An object of the present invention, which has been completed byaddressing the problems discussed above, is to provide a semiconductordevice through which the junction leak current can be reduced and thereliability of the gate oxide film can be improved by minimizing divotformation and the occurrence of a kink, and a method of manufacturingthe semiconductor device.

In order to achieve the object described above, in a first aspect of thepresent invention, a semiconductor device provided with a groove-liketrench at the isolation region, with an oxide film containing nitrogenused to constitute a liner oxide film in the trench, is provided. Byusing an oxide film containing nitrogen to constitute the liner oxidefilm, the degree of distortion occurring in the structure within theoxide film can be lessened. In addition, the compressive stress in thetrench liner oxide film, the stress at the edge of the active area andthe tensile stress imparted to the Si substrate are all reduced. Thus,the formation of crystal defects, the junction leak current and theoccurrence of a kink are minimized.

In a second aspect of the present invention, a semiconductor deviceprovided with a groove-like trench located at an isolation region, withnitrogen contained in the composition of the surface of an isolationfilm within the trench, is provided. Since the HF resistance is improvedby adopting this structure, divots are less likely to be formed duringthe subsequent HF process.

In a third aspect of the present invention, a semiconductor deviceprovided with a groove-like trench located at an isolation region, withnitrogen contained in the composition of the surface of an isolationfilm within the trench and also in the composition of the surface of anelement formation area, is provided. Since stresses are reduced over awide range by adopting this structure, accelerated diffusion ofimpurities can be minimized, to ultimately prevent the formation ofkinks. In addition, since the HF resistance is improved, divots are lesslikely to be formed during the subsequent HF process.

In a fourth aspect of the present invention, a semiconductor devicemanufacturing method comprising a step in which a pad oxide film and asilicon nitride film are formed on an Si substrate, a step in which agroove-like trench is formed through photolithography and etching, astep in which the liner oxide of the trench are oxidized by employing anoxidizing-nitriding method and a step in which the trench is filled withan insulating film and then after planarization, the silicon nitridefilm and the pad oxide film are removed, is provided. By using an oxidefilm containing nitrogen, the degree to which the structure within theoxide film becomes distorted can be lessened, so that the compressivestress occurring inside the trench liner oxide film, the stressoccurring at the edge of the active area and the tensile stress impartedto the Si substrate are reduced to minimize the occurrence of crystaldefects formation, junction leak current and the occurrence of a kink.

In addition, in a fifth aspect of the present invention, a semiconductordevice manufacturing method comprising a step in which a pad oxide filmand a silicon nitride film are formed on an Si substrate, a step inwhich a groove-like trench is formed through photolithography andetching, a step in which the insidewalls of the trench are oxidized, astep in which the trench is filled with an insulating film and thenafter planarization, the silicon nitride film and the pad oxide film areremoved and a step in which after sacrificial oxidation is implementedthrough oxidizing-nitriding, ion implantation is performed, is provided.Since the HF resistance of the isolation film is improved by employingthis method, divot formation is minimized. In addition, in a sixthaspect of the present invention, by oxidizing the trench insidewallsthrough oxidizing-nitriding, the surface area at the boundary with theSi substrate is strengthened to further inhibit formation of divots.

In a seventh aspect of the present invention, a semiconductor devicemanufacturing method comprising a step in which a pad oxide film and asilicon nitride film are formed on an Si substrate, a step in which agroove-like trench is formed through photolithography and etching, astep in which the insidewalls of the trench are oxidized by employing anoxidizing-nitriding method, a step in which the trench is filled with aninsulating film and then after planarization, the silicon nitride filmand the pad oxide film are removed and a step in which gate oxidation isimplemented through oxidizing-nitriding and ion implantation isperformed, is provided. A high degree of HF resistance is achieved andalso the entire manufacturing process is shortened in addition toachieving an improvement in the reliability of the gate oxide film byemploying this manufacturing method.

In a eighth aspect of the present invention, a semiconductor devicemanufacturing method comprising a step in which a pad oxide filmconstituted of a TEOS-type CVD oxide film is formed on an Si substrate,the pad oxide film thus formed is annealed through the RTA method andthen a silicon nitride film is formed over the annealed pad oxide film,a step in which a groove-like trench is formed through photolithographyand etching, a step in which the trench insidewalls are oxidized byemploying an oxidizing-nitriding method, a step in which the trench isfilled with an insulating film and then the silicon nitride film and thepad oxide film are removed after planarization and a step in which gateoxidation is implemented through oxidizing-nitriding and then ionimplantation is performed, is provided. By using a CVD oxide film withlow HF resistance to constitute the pad oxide film, the pad oxide filmcan be removed quickly, and since this results in a reduction in thequantity of embedded insulating film that is removed, divot formation isminimized.

In an ninth aspect of the present invention, a semiconductor devicemanufacturing method comprising a step in which a pad oxide filmconstituted of a TEOS-type CVD oxide film is formed on an Si substrate,the pad oxide film thus formed is annealed through the RTA method andthen a silicon nitride film is formed over the annealed pad oxide film,a step in which photolithography and etching are performed and asacrificial LOCOS is formed through oxidizing-nitriding, a step in whicha groove-like trench is formed within the LOCOS area, through etching, astep in which the trench insidewalls are oxidized by employing anoxidizing-nitriding method, a step in which the trench is filled with aninsulating film and then the silicon nitride film and the pad oxide filmare removed after planarization and a step in which gate oxidation isimplemented through oxidizing-nitriding and then ion implementation isperformed, is provided. Since the oxide film containing nitrogen remainsas part of the LOCOS, the HF resistance is improved to minimize divotformation. Furthermore, through the formation of the LOCOS, the cornersof the edges of the active area become rounded to prevent a reduction inthe thickness of the gate oxide film.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features of the invention and the concomitantadvantages will be better understood and appreciated by persons skilledin the field to which the invention pertains in view of the followingdescription given in conjunction with the accompanying drawings whichillustrate preferred embodiments.

FIG. 1 presents sectional views of the semiconductor manufacturing stepsin a first embodiment of the present invention;

FIG. 2 presents sectional views of the semiconductor manufacturing stepsin a second embodiment of the present invention;

FIG. 3 presents sectional views of the semiconductor manufacturing stepsin a third embodiment of the present invention;

FIG. 4 presents sectional views of the semiconductor manufacturing stepsin a fourth embodiment of the present invention;

FIG. 5 presents sectional views of the semiconductor manufacturing stepsin a fifth embodiment of the present invention;

FIG. 6 presents sectional views of the semiconductor manufacturing stepsin a sixth embodiment of the present invention;

FIG. 7 illustrates the trench structure;

FIG. 8 is an enlarged view of the area around the edge of an activearea; and

FIG. 9 is the transistor characteristics curve resulting from theformation of a parasitic transistor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following is a detailed explanation of the preferred embodiments ofthe present invention, given in reference to the drawings. FIG. 1presents sectional views of the semiconductor device manufacturing stepsin the first embodiment of the present invention.

-   1) First, as illustrated in FIG. 1(a), a pad oxide film 3 is formed    to a thickness of 100-300 angstroms on an Si substrate 1 in a wet O2    atmosphere at 850 degrees centigrade. Over the pad oxide film 3 thus    formed, an Si3N4 film 5 is formed to a thickness of 1500-2000    angstroms through LPCVD (low pressure CVD).-   2) Next, a photolithography process is performed and the Si3N4 film    5 is etched through the RIE (reactive ion etching) method. With a    resist applied, the Si substrate 1 is etched by using the Si3N4 film    5 as a mask and the resist is removed to form a trench 7.-   3) As shown in FIG. 1(b), a trench liner oxide film 9 is formed to a    thickness of 300 angstroms by employing the RTA (rapid thermal    anneal) method in which oxidizing/nitriding is performed by first    implementing oxidation in an O2 atmosphere at 1050˜1150 degrees    centigrade, implementing nitriding in an NH3 atmosphere at 950˜1050    degrees centigrade and implementing reoxidation in an N2O atmosphere    at 1050˜1150 degrees centigrade.-   4) As illustrated in FIG. 1(c), the trench is filled with a CVD    oxide film 11.-   5) As illustrated in FIG. 1(d), the CVD oxide film 11 undergoes CMP    (chemical-mechanical polishing) for planarization.-   6) As illustrated in FIG. 1(e), a field area is formed by removing    the Si3N4 film 5 and the pad oxide film 3.-   7) Subsequently, a transistor is formed by implementing specific    steps.

In this embodiment, the trench liner oxide film 9 is an oxide-nitridefilm that contains nitrogen. In an oxide film containing a specificquantity of nitrogen, the degree to which its internal structure becomesdistorted can be lessened. As a result, compressive stress occurring inthe trench liner oxide film 9 is reduced, and the stress-occurring atthe edge of the active area and the tensile stress imparted to the Sisubstrate 1 are also reduced. Consequently, since the occurrence ofcrystal defects formation in the Si substrate near the trench lineroxide is inhibited, the junction leak current is reduced. In addition,since accelerated diffusion of impurities in the vicinity of thesidewalls is minimized during the subsequent ion implantation andactivation, a parasitic transistor is less likely to form and,ultimately, the occurrence of a kink is minimized. Furthermore, the HFresistance of the trench liner oxide 9 containing nitrogen is improved.Thus, since the degree to which the edge becomes corroded during thesubsequent HF process is reduced, divot formation is minimized.

FIG. 2 presents sectional views of the semiconductor manufacturing stepsin the second embodiment of the present invention. A trench is formed asin the steps explained in (1) and (2) in the first embodiment. Then, asillustrated in FIG. 2(a), a trench liner oxide film 29 is formed throughthermal oxidation implemented in a dry O2 atmosphere at 950˜1050 degreescentigrade. Subsequently, steps similar to the steps (4)˜(6) in thefirst embodiment are implemented. Those steps are illustrated in FIGS.2(b), (c) and (d).

Next, as illustrated in FIG. 2(e), a sacrificial oxide film 28 is formedthrough oxidizing/nitriding performed under similar conditions to thoseadopted in the trench oxide film formation in the first embodiment, ionimplantation is implemented to determine the threshold voltage of thetransistor and activation annealing is performed. Then, transistorformation is implemented by performing specific steps such as gateelectrode formation.

In this embodiment, an oxide-nitride film is formed in the active areaon the Si substrate 1. As explained earlier, in an oxide film containinga specific quantity of nitrogen, the degree to which its internalstructure becomes distorted can be lessened and, as a result, the stressoccurring near the surface of the Si substrate 1 is reduced. Thus,accelerated diffusion of impurities is minimized during the subsequention implantation and activation to inhibit formation of a parasitictransistor and the occurrence of a kink. In addition, since a filmcontaining nitrogen is formed at the surface of the CVD oxide film 11during the sacrificial oxidation process, the HF resistance is improvedcompared to that of a standard CVD oxide film. Since this reduces thedegree of corrosion of the CVD oxide film 11 occurring during thesubsequent HF process, divot formed is minimized.

FIG. 3 presents sectional views of the semiconductor devicemanufacturing steps in the third embodiment of the present invention. Inthis embodiment, a field area is formed by implementing steps similar tothe steps (1)-(6) in the first embodiment. Since the manufacturing stepsperformed to form the field area are the same as those presented in FIG.1, their illustration is omitted in FIG. 3. FIG. 3(a) corresponds toFIG. 1(e). Namely, the trench liner oxide film 9 in the thirdembodiment, too, is formed through oxidizing/nitriding implemented underconditions similar to those under which the trench liner oxide film 9 inthe first embodiment is formed.

Next, as illustrated in FIG. 3(b), a sacrificial oxide film 28 is formedthrough oxidizing/nitriding performed under conditions similar to thoseunder which the trench oxide film 9 in the first embodiment is formed,ion implantation is implemented to determine the threshold voltage ofthe transistor and then activation annealing is implemented. Then, atransistor is formed by implementing specific steps such as gateelectrode formation.

This embodiment, in which the trench linear oxide film 9 and thesacrificial oxide film 28 are both constituted of an oxide-nitride film,incorporates the first embodiment and the second embodiment. As aresult, advantages achieved in the two embodiments are realized. Inparticular, through the stress reducing effect explained earlier,accelerated diffusion of impurities is suppressed over a larger range.In addition, since both the trench liner oxide film .9 and thesacrificial oxide film 28 achieves an improvement in HF resistance,divot formation is prevented during subsequent HF processes even moreeffectively.

FIG. 4 presents sectional views of the semiconductor devicemanufacturing steps in the fourth embodiment of the present invention.In this embodiment, a field area is formed by implementing steps similarto the steps (1)˜(6) in the first embodiment. Since the manufacturingsteps performed to form the field area are the same as those presentedin FIG. 1, their illustration is omitted in FIG. 4. FIG. 4(a)corresponds to FIG. 1(e). Namely, the trench liner oxide film 9 in thefourth embodiment, too, is formed through oxidizing/nitridingimplemented under conditions similar to those under which the trenchliner oxide film 9 in the first embodiment is formed.

Next, as illustrated in FIG. 4(b), a gate oxide film 48 is formedthrough oxidizing/nitriding performed under conditions similar to thoseunder which the trench oxide film 9 in the first embodiment is formed,ion implantation is implemented to determine the threshold voltage ofthe transistor and then activation annealing is implemented. Then, atransistor is formed by implementing specific steps.

It has been reported that through the reoxidation implemented during anoxidizing/nitriding process, the degree to which the thickness of a gateoxide film becomes reduced at an edge of a LOCOS is lessened. Since asimilar effect is expected to manifest in a trench structure, the fourthembodiment, in which the gate oxide film 48 is formed throughoxidizing/nitriding, achieves an advantage of improved reliability ofthe gate oxide film 48 in addition to the advantages of the thirdembodiment. In the manufacturing method in the prior art, sacrificialoxidation is implemented after a field oxide film is formed, ionimplantation for determining the transistor threshold voltage isperformed and the ions are activated, then the sacrificial oxide film isremoved and then electrodes are formed after gate oxidation is performedto form a transistor. However, a in the fourth embodiment, the ionimplantation for determining the transistors threshold voltage isperformed over the gate oxide film 48 without implementing thesacrificial oxidation step. Thus, the number of manufacturing steps isreduced to save time and lower production costs, while achieving theadvantage of improved HF resistance.

FIG. 5 represents sectional views of the semiconductor devicemanufacturing steps in the fifth embodiment of the present invention.

-   1) First, as illustrated in FIG. 5(a), a pad oxide film 53    constituted of a TEOS (tetra-ethyl-ortho-silicate) type CVD oxide    film is formed to a thickness of 100˜500 angstroms on a Si substrate    1. Then, the pad oxide film 53 is annealed in an N 2 atmosphere    through the RTA method preferably at a temperature equal to the    temperature at which the trench oxide film is formed, i.e., in the    temperature rate of approximately 1000˜1050 degrees centigrade, to    harden and tighten the CVD oxide film. Next, a Si3N4 film 5 is    formed to a thickness of 1500˜2000 angstroms through LPCVD.-   2) A photolithography process is performed and the Si3N4 film 5 is    etched through the RIE method. With a resist applied, the Si    substrate 1 is etched by using the Si3N4 film 5 as a mask and the    resist is removed to form a trench 7.-   3) As shown in FIG. 5(b), a trench liner oxide film 9 is formed to a    thickness of 300 angstroms by employing the RTA method implemented    under conditions similar to those under which the trench oxide film    is formed in the first embodiment.-   4) As illustrated in FIG. 5(c), the trench is filled with the CVD    oxide film-   5) Next, CMP is performed for planarization.-   6) As illustrated in FIG. 5(d), a field area is formed by removing    the Si3N4 film 5 and the pad oxide film 53.-   7) As illustrated in FIG. 5(e), a gate oxide film 48 is formed    through oxidizing/nitriding implemented under conditions similar to    those under which the trench oxide film 9 is formed in the first    embodiment, an ion implementation for determining the transistor    threshold voltage is performed and activation annealing is    performed. Then, transistor formation is performed by following    specific steps.

In this embodiment, a CVD oxide film with lower HF resistance comparedto that of a thermal oxide film is used to constitute the pad oxide film53 and, as a result, the HF process is implemented at a higher rate toachieve a reduction in the length of time required for removing the padoxide film 53. In addition, since this results in a reduction in thedegree to which the CVD oxide film 11 is corroded when the pad oxidefilm 53 is removed, divot formation is minimized.

FIG. 6 presents sectional views of the semiconductor devicemanufacturing steps in the sixth embodiment of the present invention. Inthis embodiment, after the first step in the fifth embodiment, aphotolithography process is implemented and the Si3N4 film 5 is etchedthrough the RIE method. Then, as illustrated in FIG. 6(a), a sacrificialLOCOS 68 is formed to a thickness of approximately 100˜500 angstromsthrough oxidizing/nitriding implemented under conditions similar tothose under which the trench linear oxide film 9 in the first embodimentis formed.

Next, a photolithography process is implemented, and as illustrated inFIG. 6(b), a trench 7 is formed through etching over a specific area inthe LOCOS 68 that has been formed. Then, a trench liner oxide film 9 isformed by employing the RTA method, to a thickness of 300 angstromsthrough oxidizing/nitriding implemented under conditions similar tothose under which the trench liner oxide film 9 is formed in the firstembodiment.

Next, the trench is filled with a CVD oxide film 11 and, as illustratedin FIG. 6(c), CMP is performed for planarization. As illustrated in FIG.6(d), the S3N4 film 5 and the pad oxide film 53 are removed to form afield area. As shown in FIG. 6(e), a gate oxide film 48 is formedthrough oxidizing/nitriding as in the fifth embodiment, ionimplementation is implemented to determine the transistor thresholdvoltage and activation annealing is performed. Then, specific steps areimplemented to form a transistor.

During this process, the trench 7 may be formed after the sacrificialLOCOS 68 is formed by using the S3N4 film 5 as a mask withoutimplementing the photolithography process. In such a case, since thephotolithography process is skipped, the manufacturing method issimplified.

In this embodiment, since the remaining portion of the LOCOS 68 formedas a sacrifice constitutes an oxide film containing nitrogen, whichacthieves a higher degree of HF resistance compared to a standard CVDoxide film, divot formation is inhibited even more effectively comparedto the fifth embodiment. In addition, through the formation of the LOCOS68, the corners of the edges of the active area are rounded to prevent areduction in the film thickness of the gate oxide film 48.

While the invention has been particularly shown and described withrespect to preferred embodiments of the semiconductor device and thesemiconductor device manufacturing method according to the presentinvention by referring to the attached drawings, the present inventionis not limited to these examples and it will be understood by thoseskilled in the art that various changes in form and detail may be madetherein without departing from the spirit, scope and teaching of theinvention.

As explained in detail above, according to the present invention, asemiconductor device that achieves a reduction in junction leak currentand an improvement in the reliability of the gate oxide film byminimizing divot formation and the occurrence of a kink, and a method ofmanufacturing this semiconductor device are provided.

The entire disclosure of Japanese Patent Application No. 11-317024 filedon Nov. 8, 1999 including specification, claims, drawings and summary isincorporated herein by reference in its entirety.

1. A method of fabricating a semiconductor device, the methodcomprising: providing a substrate; forming a pad oxide film and asilicon nitride film over the substrate; forming a trench; forming aliner oxide at least in the trench by an oxidizing step, an nitridingstep and another oxidizing step; and substantially filling the trenchwith an insulating film, performing a planarizing step to remove the padoxide and the silicon nitride film that are over the substrate.
 2. Amethod of fabricating a semiconductor device, the method comprising:providing a substrate; forming a pad oxide film and a silicon nitridefilm over the substrate; forming a trench; forming a liner oxide atleast in the trench by an oxidizing step; substantially filling thetrench with an insulating film, performing a planarizing step to removethe pad oxide and the silicon nitride film that are over the substrate;forming a sacrificial oxide layer by performing an oxidizing step, anitriding step and another oxidizing step; and performing an ionimplantation step.
 3. A method of fabricating a semiconductor device,the method comprising: providing a substrate; forming a pad oxide filmand a silicon nitride film over the substrate; forming a trench; forminga liner oxide at least in the trench by an oxidizing step, an nitridingstep and another oxidizing step; and substantially filling the trenchwith an insulating film, performing a planarizing step to remove the padoxide and the silicon nitride film that are over the substrate; andforming a sacrificial oxide layer by performing an oxidizing step, anitriding step and another oxidizing step.
 4. A method of fabricating asemiconductor device, the method comprising: providing a substrate;forming a pad oxide film and a silicon nitride film over the substrate;forming a trench; forming a liner oxide at least in the trench by anoxidizing step, an nitriding step and another oxidizing step; andsubstantially filling the trench with an insulating film, performing aplanarizing step to remove the pad oxide and the silicon nitride filmthat are over the substrate; and forming a gate oxide by an oxidizingstep, a nitriding step and another oxidizing step.
 5. A method offabricating a semiconductor device, the method comprising: providing asubstrate; chemical vapor depositing a TEOS pad oxide film over thesubstrate and annealing the pad oxide film by a rapid thermal annealstep forming a silicon nitride film over the pad oxide; forming atrench; forming a liner oxide at least in the trench by an oxidizingstep, an nitriding step and another oxidizing step; and substantiallyfilling the trench with an insulating film, performing a planarizingstep to remove the pad oxide and the silicon nitride film that are overthe substrate; and forming gate oxide layer by performing an oxidizingstep, a nitriding step and another oxidizing step.
 6. A method offabricating a semiconductor device, the method comprising: providing asubstrate; chemical vapor depositing a TEOS pad oxide film over thesubstrate and annealing the pad oxide film by a rapid thermal annealstep: forming a silicon nitride film over the pad oxide; etching thesilicon nitride film after performing a photolithographic process;forming a sacrificial local oxidation of silicon layer by an oxidizingstep, a nitriding step and another oxidizing step and a nitriding step;forming a trench; forming a liner oxide at least in the trench by anoxidizing step, a nitriding step and another oxidizing step; andsubstantially filling the trench with an insulating film, performing aplanarizing step to remove the pad oxide and the silicon nitride filmthat are over the substrate; and forming gate oxide layer by performingan oxidizing step, a nitriding step and another oxidizing step.